Pseudo random optimized built-in self-test

ABSTRACT

Test apparatus provides both flat pseudo random test patterns in combination with weighted pseudo random test patterns that the weight applied to every latch in the LSSD chain can be changed on every cycle. This apparatus fully integrates on-chip weighted pattern generation with either internal or external weight set selection. With WRP test technology, the WRP patterns are generated by the tester either externally or internally to the DUT and loaded via the shift register inputs (SRIs or WPIs) into the chip&#39;s shift register latches (SRLs). A test (or LSSD tester loop sequence) includes loading the SRLs in the SR chains with a WRP, pulsing the appropriate clocks, and unloading the responses captured in the SRLs into the multiple input signature register (MISR). Each test can then be applied multiple times for each weight set, with the weight-set assigning a weight factor or probability to each SRL. The weight factor is typically of binary granularity with probabilities of:  
     P{“1”}=[0, . . . ⅛, ¼, ½, ¾,⅞, . . . or 1] for similarly for p{0}.  
     With the above arrangement, only specific subsets of SRLs of the LSSD chain need to be weighted with each weight-set. The remaining SRLs, those not included in the weighted subset, can be loaded with “flat” pseudo-random patterns generated by the built-in LFSR. Furthermore, multiple sets of weights and associated with multiple subsets of SRLs and also be used. From “none” to “all” the latches in the array can be modified on each scan shift cycle.

CROSS REFERENCE TO RELATED PATENTS

[0001] U.S. Pat. No. 4,503,537 of common assignee herewith, issued Mar.5, 1985, and incorporated herein by reference.

[0002] U.S. Pat. No. 4,513,418 of common assignee herewith, issued Apr.23, 1985, and incorporated herein by reference.

[0003] U.S. Pat. No. 4,688,223 of common assignee herewith, issued Aug.18, 1987, and incorporated herein by reference.

[0004] U.S. Pat. No. 4,745,355 of common assignee herewith, issued May17, 1988, and incorporated herein by reference.

[0005] U.S. Pat. No. 4,801,870 of common assignee herewith, issued Jan.31, 1989, and incorporated herein by reference.

[0006] U.S. Pat. No. 5,983,380 of common assignee herewith, issued Nov.9, 1999 and incorporated herein by reference.

FIELD OF THE INVENTION

[0007] This invention relates to integrated circuits having logiccircuits and self-test circuits for testing the logic circuits andmethods performed in integrated circuits for testing the logic circuits.

BACKGROUND OF THE INVENTION

[0008] BIST (Built In Self Test), WRP (Weighted Random Pattern), anddeterministic pattern test methodologies have evolved mainly in supportof LSSD logic and structural testing, which is today the prevailing maindesign and test approach. FIG. 1 illustrates a typical testing system 10and chip design that incorporates these test methodologies. Thisstructure utilizes a Linear Feedback Shift Register (LFSR) 12 whichapplies test vectors by the LFSR 12 to shift register chains 128 to 136in an integrated circuit device under test (DUT) 14. The outputs of theshift register chains DUT 14 are inputted into a Multiple Input ShiftRegister (MISR) 16.

[0009] These test methodologies allow for three distinct test modes. Thefirst mode is based on deterministic LSSD and test techniques as shownand described in U.S. Pat. No. 3,783,254. It is fully compatible withthe original structural test modes used since the early development ofLSSD. In this mode the tester supplies the patterns to be loaded in eachSRL (Shift Register Latches) chain and then pulses the appropriatesystem clocks. The problem encountered with this approach is that thegeneration and storage (at the tester) of the deterministic patterns isrelatively expensive.

[0010] To overcome this problem, the WRP methodology was developed. Thissecond test mode utilizes a Linear Feedback Shift Register (LFSR) toalgorithmically generate a set of pseudo random test patterns at thetester as shown and described in U.S. Pat. Nos. 4,688,223, 4,745,355 and4,801,870. These patterns are then biased or weighted to optimize themfor a specific logic design. In addition, a Multiple Input SignatureRegister (MISR) is used to compress the DUT responses into a signaturefor eventual comparison to a predetermined good signature. Although thisapproach has advantages in test pattern volumes and generation cost, itrequires special tester hardware.

[0011] The third test mode is based on extending some of thesetechniques to BIST and incorporates the LFSR and MISR in the DUT. Theadvantage of this approach is that it lessens the dependency on externaltest hardware support. The problem encountered here is that the patternsgenerated by the LFSR are “flat random” patterns that usually result inrelatively low test coverage or excessive test time.

[0012] As shown in FIG. 1, in the above mentioned U.S. Pat. No.5,983,380, the self-test circuits, the pseudo random pattern generatorfor generating the pseudo random patterns includes weighting circuits118 to 126 for weighting pseudo random patterns. The weighting circuitsinclude an input 140 for receiving a weighting instruction forselectively weighting the pseudo random pattern so that the weightingcircuit and the pseudo random pattern generator generate a globalweighted pseudo random pattern for testing the logic circuits.

BRIEF DESCRIPTIONS OF THE INVENTION

[0013] In accordance with the present invention, test apparatus providesboth flat pseudo random test patterns in combination with weightedpseudo random test patterns so that the weight applied to every latch inthe LSSD chain can be changed on every cycle. This apparatus fullyintegrates on-chip weighted pattern generation with either internal orexternal weight selection. With WRP test technology, the WRP patternsare generated by the tester either externally or internally to the DUTand loaded via the shift register inputs (SRIs or WPIs) into the chip'sshift register latches (SRLs). A test (or LSSD tester loop sequence)includes loading the SRLs in the SR chains with a WRP, pulsing theappropriate clocks, and unloading the responses captured in the SRLsinto the multiple input signature register (MISR). Each test can then beapplied multiple times for each weight set, with the weight-setassigning a weight factor or probability to each SRL. The weight factoris typically of binary granularity with probabilities of:

[0014] p{“1”}=[0, . . . ⅛, ¼, ½, ¾,⅞, . . . or 1] for similarly forp{0}.

[0015] With the above arrangement, only specific subsets of SRLs of theLSSD chain need to be weighted with each weight-set. The remaining SRLs,those not included in the weighted subset, can be loaded with “flat”pseudo-random patterns generated by the built-in LFSR. Furthermore,multiple sets of weights and associated with multiple subsets of SRLsand also be used. From “none” to “all” the latches in the array can bemodified on each scan shift cycle.

[0016] The new concept is compatible with existing test modes andextends the configuration, shown in FIG. 1, by incorporating supportfunctions to: allow individual weighting a subset of SRLs; internallyand/or externally apply specific weighting functions; onboard weightedrandom patterns generation; and combine “flat” pseudo random patternswith weighted and deterministic patterns.

[0017] The concept is further based on design and test ground rules thatminimize the impact to system performance, circuit overhead, andmaintains compatibility to existing structural scan configurations with:minimal impact to system functional paths; no modification to systemclocks; transitional fault coverage support; and compatibility with OPCGand LBIST control.

[0018] Therefore it is an object of the present invention to provideimproved chip testing apparatus. It is another object of the presentinvention to provide on-chip testing apparatus with improved testpattern capability.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] These and other objects of the present invention can best beunderstood from the following detailed description of embodiments of theinvention while referring to the accompany figures of which:

[0020]FIG. 1 is a block diagram illustrating a prior art on-chip testingconfiguration;

[0021]FIG. 2 is a block diagram illustrating an on-chip testingstructure according to the present invention;

[0022]FIG. 3 is a block diagram containing a more detailed view of amultipart register array of the type shown in FIG. 2;

[0023]FIG. 4 is a block diagram illustrating the weight selectionstructures of FIG. 3;

[0024]FIG. 5 is a block diagram containing a more detailed view oflatches used in FIG. 3;

[0025]FIG. 6 is a timing diagram for the latches in FIG. 5;

[0026]FIG. 7 is a flow diagram illustrating operation of the function ofFIG. 3; and

[0027]FIGS. 8 and 9 are block diagrams illustrating alternativeembodiments to the externally selectable structure of FIG. 3.

DETAILED DESCRIPTION OF THE INVENTION

[0028] As shown in FIG. 2, a multipaht register array 200 is placedbetween the LFSR and the scan chain inputs 202. The linear feedbackshift register (LFSR) 125, the SRLs 128 to 136 and the signatureanalysis shift register (MISR) 16 remain unchanged from that of FIG. 1.The register array can be an independent memory macro, an array registerstructure of individual latches 208, as shown here in FIG. 2, or anarray structure formed using a first SRL 208 of each scan chain, asshown in FIG. 3. In any case, register array 200 has a storage elementfor each scan chain 128 to 136 that can be fully loaded directly fromthe LFSR 125 and individually loaded from the array port 210. As can beseen in FIGS. 2, 8 and 9, test support structure for the LBIST engine212 can be located off chip, partially on-chip, or fully on chip,respectively. Therefore it can be seen that hardware implementation ofthe present invention is relatively simple, requires very low circuitoverhead, and can be easily incorporated into any number of existingprior art structures including the structure of FIG. 1.

[0029] Referring now to FIG. 3, linear feedback shift register 12 isutilized to supply flat pseudo random patterns to weight generators 302,304, 306 and 308. The output of these feed BS chain 328, STCM chain 320and SRL chains 332, 334, respectively.

[0030]FIG. 4 shows in somewhat more detail the weighted random pattern(WRP) generators supporting each chain 128, 130, 132, and 136. For thepurposes of illustration, a configuration with four pairs of WRPs (0,1),(¼, ¾), (⅛, ⅞), and (½, ½) have been selected. Of course one is notlimited to only four WRP values nor these specific values. Each WRP,such as generator 302 shown, receives weight select data 402, a weightgenerator or WRP generation function block, a 4:1 MUX 404 having aselection input tied to register 12 and an XORd circuit 406 to selecttrue or complement values.

[0031]FIG. 5 is a more detailed view of the latches in any two latchesin the scan chains 128 to 136 of FIG. 3. During a data loadingoperation, the first L1 stage in each latch SRL 1, in each chain isactivated by the A-clk through OR circuit 310 to receive data from oneof the weighting circuits 302 to 308. The data from the L1 stage of thelatch is then transferred to the L2 stage by activation of the b-clk toload all second stages with the data received from the weightingcircuits. In addition to this simultaneous loading of all SRL1 latches,each of the latches can be individually changed. For this purpose, eachof the SRL1 latches contains an AND circuit 312 which enters data fromthe latch on the concurrence of the outputs of the address MUX 314 andthe w-clock to selectively enter data into any one of the SRL1 latchesto enable data to be entered into any latch individually.

[0032]FIG. 6 is a flow diagram showing entry of a typical LSSD scansequence using the a-clk followed by the b-clk with the additionalcapability of optionally extending the cycle at location 600 between thea clock and b clock and introducing one or more update cycles using theoutput of the MUX 314 and the w-clk as shown at 602.

[0033] As shown from the flow diagram of FIG. 7, the basic loadingsequence for the latches is as follows:

[0034] 1. Generate the next LFSR pseudo random pattern (this can becombined with the previous scan cycle (step 700).

[0035] 2. Applying the L1 scan clock (a-clk) to load all the L1 latchesof the register array with pseudo random data from the LFSR (Step 702).

[0036] 3. Updating an L1 in any specific SRL1 via the register arrayport (by addressing the particular L1 latch stage and applying thew-clock (step 704).

[0037] 4. Loading the L2 latch from the L1 latch (b-clk) (step 706).

[0038] 5. Repeat steps 700 to 706 until the longest STUMPS scan chain isloaded (step 708).

[0039]FIG. 2 depicts the minimal on-chip LBIST engine support anddepends on the off-chip test system to provide the scan sequencingcontrol along with the weighted data, SRL addressing, and scan cycleupdate locations or counts. This is referred to as the “external Mode”since most of the scan data and control is external to the device undertest. This approach is compatible with design and test methodologiesthat do not incorporate full BIST support, but utilize the STUMPSarchitecture. Furthermore, this approach does not require special testerhardware support, such as WRP to support quasi-weighted random patterns(0, 1, ½ weights).

[0040]FIG. 8 depicts a mode that is the combination of external testersupport and internal BIST supported functions. This mode is referred toas the “internal-external mode”. In this configuration, the internalLBIST engine 212 controls the scan sequence and clocking, while thetester provides the individual SRL update. In this embodiment, the “scancycle update array” 802 provides the LBIST engine with the scan cyclethat requires one or more SRLs to be updated. The LBIST engine 212 stopsat each of these scan cycle locations and request the tester 800 toupdate all the desired SRLs. At completion of the SRL update, the testerrestarts the LBIST engine. The tester “scan cycle update sequencer”updates each SRL across the SRL chains by sequencing through the “SRaddress and data array” and issuing a w-clk on each update cycle.

[0041]FIG. 9 depicts the fully LBIST integrated support. This isreferred to as the “internal STCM mode” since the data and sequencingfunction are performed without tester support. In this mode, both theSRL update address and data and the scan cycle location data ispre-loaded in the onboard arrays 802 and 900. The LBIST engine isfurther modified with an additional comparator that provides the scancycle stopping capability from the sequencing control for updating theSRLs from the “SR address and data array”.

[0042] Although we have been discussing the use of this concept for VLSIchips with LBIST structures, the concept can be extended to fullyintegrated test subsystems. At this level of integration, the subsystemwould be capable of self test and self diagnosis leading to dynamic selfrepair. This could result in significant yield improvements at the uPtest level by utilizing redundancy enabling techniques.

[0043] Similarly, at the system level the benefit of self diagnosis andself repair would be realized by dynamically reconfiguring the systemand thereby minimizing system down time. A further extension of thisconcept in a large system environment would be to generate and store theexpected signatures at system bring-up time and then invoke them forsystem diagnosis when required.

[0044] The proposed solution is superior to the methods described abovebecause it provides a efficient, consolidated and unique integralsolution to the total BIST problem with the following benefits:

[0045] Integrates “flat” LBIST and WRP test methodologies.

[0046] Consolidation into a single test methodology.

[0047] Compatible with existing structural LSSD and LBIST base (STUMPS).

[0048] No effect on the chip cycle time as the functional logic path tothe latches is not affected.

[0049] Utilizes existing test system base.

[0050] Usable in system test environment.

[0051] Reduction in weighted random test data volumes.

[0052] Extendibility to fully integrated BIST and

[0053] Decrease the overall test time when integrated with embeddedarrays.

[0054] Can execute WRP at system speed.

[0055] Does not require special WRP test system hardware.

[0056] Minimizes software support for diverse ATPG and TDS systems.

[0057] Implementation is relatively simple and requires low circuitoverhead.

[0058] Furthermore, the concept allows for a simpler design supportingflat random, deterministic, and weighted random pattern test modes.

[0059] Although the present invention and its advantages have beendescribed in detail, it should be understood that various changes,substitutions and alterations can be made herein without departing fromthe spirit and scope of the invention as defined in the appended claims.

What is claimed is:
 1. An integrated circuit, comprising logic circuitsconnected to a plurality of scan chains and self-test circuits fortesting said logic circuits, said self-test circuits comprising: apseudo random pattern generator for generating at least one flat pseudorandom pattern; weighting circuits for providing a selectable weight setto said flat pseudo random patterns; a storage element associated witheach of the weighting pattern generators receipt of a random patternfrom the associated random pattern generator; and a selection circuitfor individually addressing each of the storage elements for providingsaid weighted pseudo random pattern to said scan chains independently ofone another for scanning said weighted pattern to said logic circuits toenable provision of different weights to the storage elements.
 2. Anintegrated circuit as recited in claim 1, wherein said weighting circuitcomprises a weight generating circuit and a weight selecting circuit. 3.The integrated circuit as recited in claim 1, wherein said weightingcircuit includes means for receiving a weighting instruction from anexternal source to said integrated circuit.
 4. The integrated circuit asrecited in claim 1, wherein said storage elements are each a first stageof an associated scan chain.
 5. The integrated circuit as recited inclaim 4, wherein said pseudo random pattern generator and said weightingpatterns, receipts pattern and weighting instructions from a testerinternal to said integrated circuit.
 6. The integrated circuit asrecited in claim 4, wherein said weighting instruction is generated by atester external to said integrated circuit.
 7. The integrated circuit asrecited in claim 4, further comprising a memory or register arraywherein at least a portion of said weighting instruction is stored insaid memory array.
 8. A method of testing an integrated circuit,comprising logic circuits connected to scan chains and self-testcircuits on said integrated circuit for testing said logic circuits, themethod comprising: a) generating a pseudo random pattern; b) providing aweight to said pseudo random pattern; and c) selectively providing saidweighted pseudo random pattern to at least one but not all the scanchains for scanning said weighted pattern to the logic circuits.
 9. Themethod as recited in claim 8, wherein said weighted pseudo randompattern is introduced to a portion but not all of said at least one scanchain.